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[PULL 26/31] target/riscv: cpu: Add a config option for native debug
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From: |
Alistair Francis |
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Subject: |
[PULL 26/31] target/riscv: cpu: Add a config option for native debug |
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Date: |
Thu, 21 Apr 2022 16:36:25 +1000 |
From: Bin Meng <bin.meng@windriver.com>
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421003324.1134983-3-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 4 +++-
target/riscv/cpu.c | 5 +++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 39a9ff17d3..62e53e3653 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -79,7 +79,8 @@ enum {
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
RISCV_FEATURE_MISA,
- RISCV_FEATURE_AIA
+ RISCV_FEATURE_AIA,
+ RISCV_FEATURE_DEBUG
};
/* Privileged specification version */
@@ -405,6 +406,7 @@ struct RISCVCPUConfig {
bool pmp;
bool epmp;
bool aia;
+ bool debug;
uint64_t resetvec;
};
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8919928f4f..477961b619 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -548,6 +548,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
riscv_set_feature(env, RISCV_FEATURE_AIA);
}
+ if (cpu->cfg.debug) {
+ riscv_set_feature(env, RISCV_FEATURE_DEBUG);
+ }
+
set_resetvec(env, cpu->cfg.resetvec);
/* Validate that MISA_MXL is set properly. */
@@ -795,6 +799,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
--
2.35.1
- [PULL 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0, (continued)
- [PULL 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0, Alistair Francis, 2022/04/21
- [PULL 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults, Alistair Francis, 2022/04/21
- [PULL 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM, Alistair Francis, 2022/04/21
- [PULL 19/31] target/riscv/pmp: fix NAPOT range computation overflow, Alistair Francis, 2022/04/21
- [PULL 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT, Alistair Francis, 2022/04/21
- [PULL 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled, Alistair Francis, 2022/04/21
- [PULL 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable, Alistair Francis, 2022/04/21
- [PULL 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices, Alistair Francis, 2022/04/21
- [PULL 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT, Alistair Francis, 2022/04/21
- [PULL 25/31] target/riscv: debug: Implement debug related TCGCPUOps, Alistair Francis, 2022/04/21
- [PULL 26/31] target/riscv: cpu: Add a config option for native debug,
Alistair Francis <=
- [PULL 27/31] target/riscv: csr: Hook debug CSR read/write, Alistair Francis, 2022/04/21
- [PULL 28/31] target/riscv: machine: Add debug state description, Alistair Francis, 2022/04/21
- [PULL 29/31] target/riscv: cpu: Enable native debug feature, Alistair Francis, 2022/04/21
- [PULL 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint(), Alistair Francis, 2022/04/21
- [PULL 31/31] hw/riscv: boot: Support 64bit fdt address., Alistair Francis, 2022/04/21
- Re: [PULL 00/31] riscv-to-apply queue, Richard Henderson, 2022/04/21