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[PULL 02/34] target/arm: Don't add all MIDR aliases for cores that imple
From: |
Peter Maydell |
Subject: |
[PULL 02/34] target/arm: Don't add all MIDR aliases for cores that implement PMSA |
Date: |
Thu, 5 Jan 2023 16:43:45 +0000 |
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Cores with PMSA have the MPUIR register which has the
same encoding as the MIDR alias with opc2=4. So we only
add that alias if we are not realizing a core that
implements PMSA.
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221206102504.165775-2-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bac2ea62c44..090daf93c71 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8153,10 +8153,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
.readfn = midr_read },
- /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
- { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
- .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
- .access = PL1_R, .resetvalue = cpu->midr },
+ /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
{ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
.access = PL1_R, .resetvalue = cpu->midr },
@@ -8166,6 +8163,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.accessfn = access_aa64_tid1,
.type = ARM_CP_CONST, .resetvalue = cpu->revidr },
};
+ ARMCPRegInfo id_v8_midr_alias_cp_reginfo = {
+ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
+ .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
+ .access = PL1_R, .resetvalue = cpu->midr
+ };
ARMCPRegInfo id_cp_reginfo[] = {
/* These are common to v8 and pre-v8 */
{ .name = "CTR",
@@ -8231,6 +8233,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
if (arm_feature(env, ARM_FEATURE_V8)) {
define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
+ if (!arm_feature(env, ARM_FEATURE_PMSA)) {
+ define_one_arm_cp_reg(cpu, &id_v8_midr_alias_cp_reginfo);
+ }
} else {
define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
}
--
2.25.1
- [PULL 00/34] target-arm queue, Peter Maydell, 2023/01/05
- [PULL 02/34] target/arm: Don't add all MIDR aliases for cores that implement PMSA,
Peter Maydell <=
- [PULL 01/34] target/arm:Set lg_page_size to 0 if either S1 or S2 asks for it, Peter Maydell, 2023/01/05
- [PULL 03/34] target/arm: Make RVBAR available for all ARMv8 CPUs, Peter Maydell, 2023/01/05
- [PULL 04/34] target/arm: Make stage_2_format for cache attributes optional, Peter Maydell, 2023/01/05
- [PULL 05/34] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32, Peter Maydell, 2023/01/05
- [PULL 08/34] target/arm: Add ARM Cortex-R52 CPU, Peter Maydell, 2023/01/05
- [PULL 07/34] target/arm: Add PMSAv8r functionality, Peter Maydell, 2023/01/05
- [PULL 12/34] hw/timer/imx_epit: define SR_OCIF, Peter Maydell, 2023/01/05
- [PULL 10/34] hw/timer/imx_epit: improve comments, Peter Maydell, 2023/01/05
- [PULL 13/34] hw/timer/imx_epit: update interrupt state on CR write access, Peter Maydell, 2023/01/05
- [PULL 09/34] target/arm: fix handling of HLT semihosting in system mode, Peter Maydell, 2023/01/05