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[PULL v3 39/43] hw/riscv: sifive_u: Avoid using magic number for "riscv,
From: |
Alistair Francis |
Subject: |
[PULL v3 39/43] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" |
Date: |
Fri, 6 Jan 2023 13:13:53 +1000 |
From: Bin Meng <bmeng@tinylab.org>
At present magic number is used to create "riscv,ndev" property
in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that
is used to instantiate the PLIC model instead.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-12-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b139824aab..b40a4767e2 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -287,7 +287,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry
*memmap,
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_DEV_PLIC].base,
0x0, memmap[SIFIVE_U_DEV_PLIC].size);
- qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
+ qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev",
+ SIFIVE_U_PLIC_NUM_SOURCES - 1);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
g_free(cells);
--
2.39.0
- [PULL v3 29/43] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers, (continued)
- [PULL v3 29/43] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers, Alistair Francis, 2023/01/05
- [PULL v3 30/43] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC, Alistair Francis, 2023/01/05
- [PULL v3 31/43] hw/riscv: Sort machines Kconfig options in alphabetical order, Alistair Francis, 2023/01/05
- [PULL v3 33/43] hw/intc: sifive_plic: Drop PLICMode_H, Alistair Francis, 2023/01/05
- [PULL v3 37/43] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC, Alistair Francis, 2023/01/05
- [PULL v3 34/43] hw/intc: sifive_plic: Improve robustness of the PLIC config parser, Alistair Francis, 2023/01/05
- [PULL v3 36/43] hw/intc: sifive_plic: Update "num-sources" property default value, Alistair Francis, 2023/01/05
- [PULL v3 40/43] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb, Alistair Francis, 2023/01/05
- [PULL v3 35/43] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize(), Alistair Francis, 2023/01/05
- [PULL v3 38/43] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Alistair Francis, 2023/01/05
- [PULL v3 39/43] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev",
Alistair Francis <=
- [PULL v3 41/43] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0, Alistair Francis, 2023/01/05
- [PULL v3 43/43] hw/intc: sifive_plic: Fix the pending register range check, Alistair Francis, 2023/01/05
- [PULL v3 32/43] hw/riscv: spike: Remove misleading comments, Alistair Francis, 2023/01/05
- [PULL v3 42/43] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization, Alistair Francis, 2023/01/05
- Re: [PULL v3 00/43] riscv-to-apply queue, Peter Maydell, 2023/01/07