Re: [PULL v3 00/43] riscv-to-apply queue

[Peter Maydell]

On Fri, 6 Jan 2023 at 03:19, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit d1852caab131ea898134fdcea8c14bc2ee75fbe9:
>
>   Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into 
> staging (2023-01-05 16:59:22 +0000)
>
> are available in the Git repository at:
>
>   https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230106
>
> for you to fetch changes up to bc92f261519d5c77c70cf2ebcf0a3b9a414d82d0:
>
>   hw/intc: sifive_plic: Fix the pending register range check (2023-01-06 
> 10:42:55 +1000)
>
> ----------------------------------------------------------------
> First RISC-V PR for QEMU 8.0
>
> * Fix PMP propagation for tlb
> * Collection of bug fixes
> * Bump the OpenTitan supported version
> * Add smstateen support
> * Support native debug icount trigger
> * Remove the redundant ipi-id property in the virt machine
> * Support cache-related PMU events in virtual mode
> * Add some missing PolarFire SoC io regions
> * Fix mret exception cause when no pmp rule is configured
> * Fix bug where disabling compressed instructions would crash QEMU
> * Add Zawrs ISA extension support
> * A range of code refactoring and cleanups



Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.

-- PMM