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[PULL v3 32/43] hw/riscv: spike: Remove misleading comments
From: |
Alistair Francis |
Subject: |
[PULL v3 32/43] hw/riscv: spike: Remove misleading comments |
Date: |
Fri, 6 Jan 2023 13:13:46 +1000 |
From: Bin Meng <bmeng@tinylab.org>
PLIC is not included in the 'spike' machine.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-5-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/spike.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 1e1d752c00..13946acf0d 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -8,7 +8,6 @@
*
* 0) HTIF Console and Poweroff
* 1) CLINT (Timer and IPI)
- * 2) PLIC (Platform Level Interrupt Controller)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
--
2.39.0
- [PULL v3 33/43] hw/intc: sifive_plic: Drop PLICMode_H, (continued)
- [PULL v3 33/43] hw/intc: sifive_plic: Drop PLICMode_H, Alistair Francis, 2023/01/05
- [PULL v3 37/43] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC, Alistair Francis, 2023/01/05
- [PULL v3 34/43] hw/intc: sifive_plic: Improve robustness of the PLIC config parser, Alistair Francis, 2023/01/05
- [PULL v3 36/43] hw/intc: sifive_plic: Update "num-sources" property default value, Alistair Francis, 2023/01/05
- [PULL v3 40/43] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb, Alistair Francis, 2023/01/05
- [PULL v3 35/43] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize(), Alistair Francis, 2023/01/05
- [PULL v3 38/43] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Alistair Francis, 2023/01/05
- [PULL v3 39/43] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev", Alistair Francis, 2023/01/05
- [PULL v3 41/43] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0, Alistair Francis, 2023/01/05
- [PULL v3 43/43] hw/intc: sifive_plic: Fix the pending register range check, Alistair Francis, 2023/01/05
- [PULL v3 32/43] hw/riscv: spike: Remove misleading comments,
Alistair Francis <=
- [PULL v3 42/43] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization, Alistair Francis, 2023/01/05
- Re: [PULL v3 00/43] riscv-to-apply queue, Peter Maydell, 2023/01/07