[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-ppc] [Qemu-devel] Incorrect handling of more PPC64 insns (PATC

From: Alexander Graf
Subject: Re: [Qemu-ppc] [Qemu-devel] Incorrect handling of more PPC64 insns (PATCH)
Date: Wed, 8 May 2013 11:32:49 +0200

On 08.05.2013, at 11:20, Torbjorn Granlund wrote:

> Aurelien Jarno <address@hidden> writes:
>  64-bit CPUs check for the L bit of comparison instruction to determine
>  if the instruction is 32-bit wide, and not to the MSR SF bit.
>  L=1 on a 32-bit CPU should generate an invalid instruction exception.
> No.  See my previous post.
> The L bit is to be ignored for 32-bit CPUs, just like the original code
> did.

I see. So if the target is 64bit capable, then we distinguish by the 
instruction bit, but for 32bit targets we always call the 32bit variant 
regardless of the bit?


reply via email to

[Prev in Thread] Current Thread [Next in Thread]