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Re: [Qemu-ppc] [Qemu-devel] Incorrect handling of more PPC64 insns (PATC

From: Alexander Graf
Subject: Re: [Qemu-ppc] [Qemu-devel] Incorrect handling of more PPC64 insns (PATCH)
Date: Wed, 8 May 2013 12:45:30 +0200

On 08.05.2013, at 12:07, Torbjorn Granlund wrote:

> Alexander Graf <address@hidden> writes:
>  Ok, so the real problem here is that NARROW_MODE is not set, but is
>  used to differentiate whether to use the 32bit cmp only or not.
> Eh?
>  Richard, there are 2 ways out of this:
>    1) get rid of NARROW_MODE and always check ctx->sf
> No!
> The cmp insn with L set should NOT be affected by SF.  That's the entire
> point of my change.

You're right. I got confused there :).

> I reviewed the other uses of NARROW_MODE and didn't spot any errors.
> (But I must confess that I would need to red the PPC manuals better inn
> order to tell for sure.)
>    2) add a new 32bit only insns flag and create separate functions for 32bit 
> cmp calls
> Aurelien's patch looked promising, if one removes the exception casting.

His exception casting is actually correct. You can use qemu-(system-)ppc64, but 
run it with a CPU definition that is 32bit only, like a G3. These old CPUs did 
not know the instruction with L yet, so they do throw an illegal instruction 
exception, which we have to model.


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