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qemu-riscv (date)
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Last Modified: Mon Nov 30 2020 22:30:24 -0500
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November 30, 2020
[PATCH 1/1] target-riscv: support QMP dump-guest-memory
,
Yifei Jiang
,
22:30
[PATCH 0/1] target-riscv: support QMP dump-guest-memory
,
Yifei Jiang
,
22:30
Re: [PATCH] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
,
Alistair Francis
,
21:22
Re: [PATCH] target/riscv: Fix the bug of HLVX/HLV/HSV
,
Alistair Francis
,
21:16
[PATCH] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
,
Alex Richardson
,
12:02
November 29, 2020
[PATCH] target/riscv: Fix the bug of HLVX/HLV/HSV
,
Yifei Jiang
,
20:28
November 27, 2020
Re: [PATCH v2 5/6] Remove unnecessary usage of arch_init.h
,
Cornelia Huck
,
07:23
Re: [PATCH v2 1/6] arch_init: Move QEMU_ARCH definitions to cpu.h
,
Cornelia Huck
,
06:36
November 26, 2020
Re: [PATCH v2 1/6] arch_init: Move QEMU_ARCH definitions to cpu.h
,
Thomas Huth
,
07:32
November 25, 2020
Re: [PATCH 1/1] hw/riscv: clint: timebase-freq is machine-specific
,
Palmer Dabbelt
,
20:32
[PATCH 4/8] semihosting: Support SYS_HEAPINFO when env->boot_info is not set
,
Keith Packard
,
16:36
[PATCH 6/8] semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ
,
Keith Packard
,
16:36
[PATCH 8/8] semihosting: Implement SYS_ISERROR
,
Keith Packard
,
16:36
[PATCH 3/8] semihosting: Change internal common-semi interfaces to use CPUState * [v2]
,
Keith Packard
,
16:36
[PATCH 7/8] semihosting: Implement SYS_TMPNAM
,
Keith Packard
,
16:36
[PATCH 5/8] riscv: Add semihosting support [v13]
,
Keith Packard
,
16:36
[PATCH 1/8] semihosting: Move ARM semihosting code to shared directories [v3]
,
Keith Packard
,
16:36
[PATCH 2/8] semihosting: Change common-semi API to be architecture-independent
,
Keith Packard
,
16:36
[PATCH 0/8] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0
,
Keith Packard
,
16:36
[PATCH v2 5/6] Remove unnecessary usage of arch_init.h
,
Eduardo Habkost
,
15:57
[PATCH v2 1/6] arch_init: Move QEMU_ARCH definitions to cpu.h
,
Eduardo Habkost
,
15:57
November 22, 2020
Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line
,
Frank Chang
,
20:22
November 20, 2020
Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line
,
Alistair Francis
,
11:25
Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line
,
Kito Cheng
,
02:15
November 19, 2020
Re: [RFC 00/15] support subsets of bitmanip extension
,
Frank Chang
,
20:45
Re: [RFC 00/15] support subsets of bitmanip extension
,
Richard Henderson
,
17:27
Re: [RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend
,
Richard Henderson
,
17:15
Re: [RFC 13/15] target/riscv: rvb: address calculation
,
Richard Henderson
,
16:38
Re: [RFC 12/15] target/riscv: rvb: generalized or-combine
,
Richard Henderson
,
16:28
Re: [RFC 11/15] target/riscv: rvb: generalized reverse
,
Richard Henderson
,
16:24
Re: [RFC 10/15] target/riscv: rvb: rotate (left/right)
,
Richard Henderson
,
16:07
Re: [RFC 08/15] target/riscv: rvb: single-bit instructions
,
Richard Henderson
,
16:04
Re: [RFC 09/15] target/riscv: rvb: shift ones
,
Richard Henderson
,
15:55
Re: [RFC 08/15] target/riscv: rvb: single-bit instructions
,
Richard Henderson
,
15:35
Re: [RFC 08/15] target/riscv: rvb: single-bit instructions
,
Richard Henderson
,
15:06
Re: [RFC 07/15] target/riscv: rvb: sign-extend instructions
,
Richard Henderson
,
14:48
Re: [RFC 02/15] target/riscv: rvb: count leading/trailing zeros
,
Richard Henderson
,
14:48
Re: [RFC 06/15] target/riscv: rvb: min/max instructions
,
Richard Henderson
,
14:46
Re: [RFC 05/15] target/riscv: rvb: pack two words into one register
,
Richard Henderson
,
14:44
Re: [RFC 04/15] target/riscv: rvb: logic-with-negate
,
Richard Henderson
,
14:28
Re: [RFC 03/15] target/riscv: rvb: count bits set
,
Richard Henderson
,
14:27
Re: [RFC 02/15] target/riscv: rvb: count leading/trailing zeros
,
Richard Henderson
,
14:24
Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line
,
Alistair Francis
,
14:06
Re: [RFC 01/15] target/riscv: reformat @sh format encoding for B-extension
,
Richard Henderson
,
14:03
November 18, 2020
[RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line
,
frank . chang
,
03:33
[RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend
,
frank . chang
,
03:33
[RFC 13/15] target/riscv: rvb: address calculation
,
frank . chang
,
03:33
[RFC 12/15] target/riscv: rvb: generalized or-combine
,
frank . chang
,
03:33
[RFC 11/15] target/riscv: rvb: generalized reverse
,
frank . chang
,
03:33
[RFC 10/15] target/riscv: rvb: rotate (left/right)
,
frank . chang
,
03:32
[RFC 09/15] target/riscv: rvb: shift ones
,
frank . chang
,
03:32
[RFC 08/15] target/riscv: rvb: single-bit instructions
,
frank . chang
,
03:32
[RFC 07/15] target/riscv: rvb: sign-extend instructions
,
frank . chang
,
03:32
[RFC 06/15] target/riscv: rvb: min/max instructions
,
frank . chang
,
03:32
[RFC 05/15] target/riscv: rvb: pack two words into one register
,
frank . chang
,
03:32
[RFC 04/15] target/riscv: rvb: logic-with-negate
,
frank . chang
,
03:32
[RFC 03/15] target/riscv: rvb: count bits set
,
frank . chang
,
03:32
[RFC 02/15] target/riscv: rvb: count leading/trailing zeros
,
frank . chang
,
03:32
[RFC 01/15] target/riscv: reformat @sh format encoding for B-extension
,
frank . chang
,
03:32
[RFC 00/15] support subsets of bitmanip extension
,
frank . chang
,
03:32
November 16, 2020
Re: [PATCH 0/1] CLINT timebase frequency is invalid for sifive machines
,
Emmanuel Blot
,
06:43
November 14, 2020
Re: Re: [PATCH] drivers: rtc: retire RTC_DRV_GOLDFISH
,
Roman Kiryanov
,
20:38
Re: Re: [PATCH] drivers: rtc: retire RTC_DRV_GOLDFISH
,
Greg KH
,
08:54
Re: Re: [PATCH] drivers: rtc: retire RTC_DRV_GOLDFISH
,
Jiaxun Yang
,
08:54
November 11, 2020
[PATCH v1 2/2] intc/ibex_plic: Ensure we don't loose interrupts
,
Alistair Francis
,
18:25
[PATCH v1 1/2] intc/ibex_plic: Fix some typos in the comments
,
Alistair Francis
,
18:25
Re: [PATCH 3/4] semihosting: Change internal common-semi interfaces to use CPUState *
,
Keith Packard
,
17:55
Re: [PATCH 4/4] riscv: Add semihosting support [v11]
,
Keith Packard
,
17:49
Re: [PATCH 3/4] semihosting: Change internal common-semi interfaces to use CPUState *
,
Alistair Francis
,
17:41
Re: [PATCH 4/4] riscv: Add semihosting support [v11]
,
Alistair Francis
,
17:31
Re: [PATCH 2/4] semihosting: Change common-semi API to be architecture-independent
,
Alistair Francis
,
17:21
Re: [PATCH] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
,
Alistair Francis
,
17:11
Re: [PATCH] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
,
Alistair Francis
,
12:02
[PATCH] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
,
Anup Patel
,
04:48
November 10, 2020
Re: [PATCH 1/4] semihosting: Move ARM semihosting code to shared directories [v3]
,
Keith Packard
,
00:25
November 09, 2020
Re: [RFC v5 00/68] support vector extension v1.0
,
Alistair Francis
,
23:13
Re: [RFC v5 00/68] support vector extension v1.0
,
Frank Chang
,
21:09
Re: [PATCH v2 4/4] hw/riscv: Load the kernel after the firmware
,
Alistair Francis
,
18:32
Re: [PATCH 1/4] semihosting: Move ARM semihosting code to shared directories [v3]
,
Alistair Francis
,
18:30
Re: [PATCH v1 1/1] hw/intc/ibex_plic: Clear the claim register when read
,
Alistair Francis
,
18:23
November 06, 2020
Re: [PATCH v1 1/1] hw/intc/ibex_plic: Clear the claim register when read
,
Philippe Mathieu-Daudé
,
09:20
Re: [RFC PATCH 02/15] hw/riscv: migrate fdt field to generic MachineState
,
Bin Meng
,
06:32
Re: [RFC PATCH 02/15] hw/riscv: migrate fdt field to generic MachineState
,
Alex Bennée
,
05:21
November 05, 2020
RE: [PATCH v2 4/4] hw/riscv: Load the kernel after the firmware
,
Anup Patel
,
23:15
Re: [RFC PATCH 02/15] hw/riscv: migrate fdt field to generic MachineState
,
Bin Meng
,
22:15
Re: [PATCH v2 4/4] hw/riscv: Load the kernel after the firmware
,
Palmer Dabbelt
,
21:48
[PATCH v1 1/1] hw/intc/ibex_plic: Clear the claim register when read
,
Alistair Francis
,
21:44
Re: [RFC PATCH 02/15] hw/riscv: migrate fdt field to generic MachineState
,
Philippe Mathieu-Daudé
,
14:24
[RFC PATCH 02/15] hw/riscv: migrate fdt field to generic MachineState
,
Alex Bennée
,
12:52
November 04, 2020
Re: [PATCH v4 4/5] target/riscv: Remove the hyp load and store functions
,
Richard Henderson
,
11:30
Re: [PATCH v4 1/5] target/riscv: Add a virtualised MMU Mode
,
Richard Henderson
,
11:24
November 03, 2020
[PATCH v4 4/5] target/riscv: Remove the hyp load and store functions
,
Alistair Francis
,
23:55
[PATCH v4 5/5] target/riscv: Split the Hypervisor execute load helpers
,
Alistair Francis
,
23:55
[PATCH v4 2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses
,
Alistair Francis
,
23:55
[PATCH v4 3/5] target/riscv: Remove the HS_TWO_STAGE flag
,
Alistair Francis
,
23:55
Re: [PATCH v3 2/7] target/riscv: Add a virtualised MMU Mode
,
Alistair Francis
,
23:55
[PATCH v4 1/5] target/riscv: Add a virtualised MMU Mode
,
Alistair Francis
,
23:55
[PATCH v4 0/5] Fix the Hypervisor access functions
,
Alistair Francis
,
23:55
Re: [PATCH v3 7/7] target/riscv: Split the Hypervisor execute load helpers
,
Richard Henderson
,
15:27
Re: [PATCH v3 6/7] target/riscv: Remove the Hypervisor access check function
,
Richard Henderson
,
15:26
Re: [PATCH v3 2/7] target/riscv: Add a virtualised MMU Mode
,
Richard Henderson
,
15:20
Re: [PATCH v3 1/7] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
,
Richard Henderson
,
15:19
Re: [PATCH v3 1/7] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
,
Alistair Francis
,
15:04
[PATCH v3 7/7] target/riscv: Split the Hypervisor execute load helpers
,
Alistair Francis
,
15:02
[PATCH v3 6/7] target/riscv: Remove the Hypervisor access check function
,
Alistair Francis
,
15:02
[PATCH v3 5/7] target/riscv: Remove the hyp load and store functions
,
Alistair Francis
,
15:02
[PATCH v3 4/7] target/riscv: Remove the HS_TWO_STAGE flag
,
Alistair Francis
,
15:02
[PATCH v3 3/7] target/riscv: Set the virtualised MMU mode when doing hyp accesses
,
Alistair Francis
,
15:02
[PATCH v3 2/7] target/riscv: Add a virtualised MMU Mode
,
Alistair Francis
,
15:02
[PATCH v3 1/7] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
,
Alistair Francis
,
15:02
[PATCH v3 0/7] Fix the Hypervisor access functions
,
Alistair Francis
,
15:02
[PATCH 1/1] hw/riscv: clint: timebase-freq is machine-specific
,
Emmanuel Blot
,
10:39
[PATCH 0/1] CLINT timebase frequency is invalid for sifive machines
,
Emmanuel Blot
,
10:39
[PATCH 2/2] hw/riscv: plic: Make IRQ slot 0 part of the IRQ priority array
,
Emmanuel Blot
,
10:31
[PATCH 1/2] hw/riscv: plic: Fix highest IRQ source slot
,
Emmanuel Blot
,
10:31
[PATCH 0/2] Fix PLIC issues
,
Emmanuel Blot
,
10:31
Re: [PATCH] target/riscv/csr.c : add space before the open parenthesis '('
,
Alistair Francis
,
10:30
November 02, 2020
Re: [PATCH] target/riscv/csr.c : add space before the open parenthesis '('
,
Alistair Francis
,
12:51
Re: [PATCH v4] hw/riscv: microchip_pfsoc: Correct DDR memory map
,
Alistair Francis
,
12:50
Re: [PATCH v4] hw/riscv: microchip_pfsoc: Correct DDR memory map
,
Alistair Francis
,
11:53
November 01, 2020
[PATCH v4] hw/riscv: microchip_pfsoc: Correct DDR memory map
,
Bin Meng
,
12:06
Re: [PATCH v3] hw/riscv: microchip_pfsoc: Correct DDR memory map
,
Alistair Francis
,
11:54
Re: [PATCH v3] hw/riscv: microchip_pfsoc: Correct DDR memory map
,
Bin Meng
,
11:51
Re: [PATCH v3] hw/riscv: microchip_pfsoc: Correct DDR memory map
,
Alistair Francis
,
11:46
[PATCH v3] hw/riscv: microchip_pfsoc: Correct DDR memory map
,
Bin Meng
,
11:42
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