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Re: TCG op for 32 bit only cpu on qemu-riscv64

From: Alistair Francis
Subject: Re: TCG op for 32 bit only cpu on qemu-riscv64
Date: Mon, 7 Jun 2021 16:22:37 +1000

On Mon, Jun 7, 2021 at 1:09 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
> Hi Alistair,
> As I see,  we are moving  on to remove TARGET_RISCV64 macro.
> I have some questions:
> 1) Which tcg op should use when translate an instruction for 32bit cpu.
> The tcg_*_i64, tcg_*_i32 or tcg_*_tl?
> I see some API such as gen_get_gpr that are using the tcg_*_tl. But I am
> not sure if it is
> right for 32bit cpu.

Do you mean for an instruction that only runs on a 32-bit CPU (and not RV64)?

If the instruction only supports a 32-bit value then tcg_*_i32
otherwise tcg_*_tl is probably the best bet.

> 2) Do we should have a sign-extend 64 bit register(bit 31 as the sign
> bit)  for 32 bit cpu?

I'm not clear what you mean. Can you point to a spec that you are
trying to implement?


> Best Regards,
> Zhiwei

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