Re: TCG op for 32 bit only cpu on qemu-riscv64

[Richard Henderson]

On 6/7/21 2:22 AM, LIU Zhiwei wrote:
> I am implementing RVP to get rid of TARGET_RISCV64. After we have recognized an 
> instruction only used by a 32-bit CPU,
>
> 1) Should we only use the lowest 32bits of the 64bits register in RV64?
>
> TCGv s;
> TCGv_i32 s32;
> s = tcg_new_temp();
> s32 = tcg_new_temp_i32();
> gen_get_gpr(src1, a->rs1);
> tcg_gen_trunc_tl_i32(s32, s);
>
> Then we can use TCGv_i32 s32  to stand for rs1 register.

Changing from _tl to _i32 is wrong for most things, because you'll just have to 
convert back in order to store the result.

Most often you'll get the correct results by just using _tl as is.  One 
operation I can think of right away which probably requires extra attention is 
right-shift.  In which case just sign- or zero-extend the input first.


r~