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Re: TCG op for 32 bit only cpu on qemu-riscv64

From: Richard Henderson
Subject: Re: TCG op for 32 bit only cpu on qemu-riscv64
Date: Mon, 7 Jun 2021 08:52:46 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1

On 6/6/21 8:07 PM, LIU Zhiwei wrote:
Hi Alistair,

As I see,  we are moving  on to remove TARGET_RISCV64 macro.

I have some questions:

1) Which tcg op should use when translate an instruction for 32bit cpu. The tcg_*_i64, tcg_*_i32 or tcg_*_tl?

You use *_tl, because that's the size of the field in CPURISCVState.

2) Do we should have a sign-extend 64 bit register(bit 31 as the sign bit)  for 32 bit cpu?

If the value must be sign-extended for RV64, then leave it sign-extended for RV32. There's no point in adding extra code to distinguish between them.

If the instruction does not exist for RV64, then you can probably leave the high bits unspecified (sign, zero, or pure garbage).


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