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Re: [PATCH v2 30/42] esp: add 4 byte PDMA read and write transfers
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From: |
Philippe Mathieu-Daudé |
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Subject: |
Re: [PATCH v2 30/42] esp: add 4 byte PDMA read and write transfers |
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Date: |
Tue, 16 Feb 2021 08:30:32 +0100 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 |
Hi Mark,
On 2/15/21 11:35 PM, Mark Cave-Ayland wrote:
> On 12/02/2021 18:56, Philippe Mathieu-Daudé wrote:
>
>> On 2/9/21 8:30 PM, Mark Cave-Ayland wrote:
>>> The MacOS toolbox ROM performs 4 byte reads/writes when transferring
>>> data to
>>> and from the target. Since the SCSI bus is 16-bits wide, use the
>>> memory API
>>> to split a 4 byte access into 2 x 2 byte accesses.
>>>
>>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>>> ---
>>> hw/scsi/esp.c | 6 ++++--
>>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>
>> Out of curiosity, what is the bus used?
>
> AFAICT it's a custom logic chip that sits on the CPU address/data buses
> that does the decoding between the CPU and ESP chip. Other than a simple
> block diagram of the Quadra there isn't much official documentation out
> there :/
OK.
> Are you planning to review any more of this series? I'm keen to put out
> a (hopefully final) v3 soon, but I'll hold off for little while if you
> want more time to look over the remaining patches.
I talked about this series with Laurent on Sunday, asking him for
review help ;) I don't remember if there is any big comment to
address in patches 1-14. If not I can review the missing ones
there today and you could send directly a pull request for this
first set, then send the rest as v3. Does that help?
For the rest I doubt having time to focus before Friday.
Regards,
Phil.
- [PATCH v2 23/42] esp: use ti_wptr/ti_rptr to manage the current FIFO position for PDMA, (continued)
- [PATCH v2 23/42] esp: use ti_wptr/ti_rptr to manage the current FIFO position for PDMA, Mark Cave-Ayland, 2021/02/09
- [PATCH v2 25/42] esp: remove CMD pdma_origin, Mark Cave-Ayland, 2021/02/09
- [PATCH v2 26/42] esp: rename get_cmd_cb() to esp_select(), Mark Cave-Ayland, 2021/02/09
- [PATCH v2 27/42] esp: fix PDMA target selection, Mark Cave-Ayland, 2021/02/09
- [PATCH v2 28/42] esp: use FIFO for PDMA transfers between initiator and device, Mark Cave-Ayland, 2021/02/09
- [PATCH v2 29/42] esp: remove pdma_origin from ESPState, Mark Cave-Ayland, 2021/02/09
- [PATCH v2 30/42] esp: add 4 byte PDMA read and write transfers, Mark Cave-Ayland, 2021/02/09
[PATCH v2 31/42] esp: implement FIFO flush command, Mark Cave-Ayland, 2021/02/09
[PATCH v2 32/42] esp: latch individual bits in ESP_RINTR register, Mark Cave-Ayland, 2021/02/09
[PATCH v2 34/42] esp: remove old deferred command completion mechanism, Mark Cave-Ayland, 2021/02/09
[PATCH v2 33/42] esp: defer command completion interrupt on incoming data transfers, Mark Cave-Ayland, 2021/02/09
[PATCH v2 35/42] esp: raise interrupt after every non-DMA byte transferred to the FIFO, Mark Cave-Ayland, 2021/02/09
[PATCH v2 37/42] esp: transition to message out phase after SATN and stop command, Mark Cave-Ayland, 2021/02/09