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[PULL 45/61] target/arm: Change DisasContext.aarch64 to bool
From: |
Peter Maydell |
Subject: |
[PULL 45/61] target/arm: Change DisasContext.aarch64 to bool |
Date: |
Fri, 22 Apr 2022 11:04:16 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Bool is a more appropriate type for this value.
Move the member down in the struct to keep the
bool type members together and remove a hole.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.h | 2 +-
target/arm/translate-a64.c | 2 +-
target/arm/translate.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 3a0db801d3b..8b7dd1a4c05 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -59,12 +59,12 @@ typedef struct DisasContext {
* so that top level loop can generate correct syndrome information.
*/
uint32_t svc_imm;
- int aarch64;
int current_el;
/* Debug target exception level for single-step exceptions */
int debug_target_el;
GHashTable *cp_regs;
uint64_t features; /* CPU features bits */
+ bool aarch64;
/* Because unallocated encodings generate different exception syndrome
* information from traps due to FP being disabled, we can't do a single
* "is fp access disabled" check at a high level in the decode tree.
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 19c09c3b535..f6303848918 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14664,7 +14664,7 @@ static void
aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->isar = &arm_cpu->isar;
dc->condjmp = 0;
- dc->aarch64 = 1;
+ dc->aarch64 = true;
/* If we are coming from secure EL0 in a system with a 32-bit EL3, then
* there is no secure EL1, so we route exceptions to EL3.
*/
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 38e7a38f280..6018fee2ef1 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9334,7 +9334,7 @@ static void arm_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
dc->isar = &cpu->isar;
dc->condjmp = 0;
- dc->aarch64 = 0;
+ dc->aarch64 = false;
/* If we are coming from secure EL0 in a system with a 32-bit EL3, then
* there is no secure EL1, so we route exceptions to EL3.
*/
--
2.25.1
- [PULL 36/61] hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi(), (continued)
- [PULL 36/61] hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi(), Peter Maydell, 2022/04/22
- [PULL 38/61] hw/intc/arm_gicv3: Allow 'revision' property to be set to 4, Peter Maydell, 2022/04/22
- [PULL 39/61] hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic(), Peter Maydell, 2022/04/22
- [PULL 28/61] hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic, Peter Maydell, 2022/04/22
- [PULL 31/61] hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi(), Peter Maydell, 2022/04/22
- [PULL 42/61] target/arm: Update ISAR fields for ARMv8.8, Peter Maydell, 2022/04/22
- [PULL 37/61] hw/intc/arm_gicv3: Update ID and feature registers for GICv4, Peter Maydell, 2022/04/22
- [PULL 30/61] hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code, Peter Maydell, 2022/04/22
- [PULL 33/61] hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling, Peter Maydell, 2022/04/22
- [PULL 40/61] hw/arm/virt: Abstract out calculation of redistributor region capacity, Peter Maydell, 2022/04/22
- [PULL 45/61] target/arm: Change DisasContext.aarch64 to bool,
Peter Maydell <=
- [PULL 43/61] target/arm: Update SCR_EL3 bits to ARMv8.8, Peter Maydell, 2022/04/22
- [PULL 44/61] target/arm: Update SCTLR bits to ARMv9.2, Peter Maydell, 2022/04/22
- [PULL 46/61] target/arm: Change CPUArchState.aarch64 to bool, Peter Maydell, 2022/04/22
- [PULL 47/61] target/arm: Extend store_cpu_offset to take field size, Peter Maydell, 2022/04/22
- [PULL 49/61] target/arm: Change CPUArchState.thumb to bool, Peter Maydell, 2022/04/22
- [PULL 50/61] target/arm: Remove fpexc32_access, Peter Maydell, 2022/04/22
- [PULL 51/61] target/arm: Split out set_btype_raw, Peter Maydell, 2022/04/22
- [PULL 53/61] target/arm: Simplify GEN_SHIFT in translate.c, Peter Maydell, 2022/04/22
- [PULL 55/61] target/arm: Simplify aa32 DISAS_WFI, Peter Maydell, 2022/04/22
- [PULL 52/61] target/arm: Split out gen_rebuild_hflags, Peter Maydell, 2022/04/22