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[PULL 44/61] target/arm: Update SCTLR bits to ARMv9.2
From: |
Peter Maydell |
Subject: |
[PULL 44/61] target/arm: Update SCTLR bits to ARMv9.2 |
Date: |
Fri, 22 Apr 2022 11:04:15 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Update SCTLR_ELx fields per ARM DDI0487 H.a.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index cc8f7f74eab..bee1cf4653a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1233,6 +1233,20 @@ void pmu_init(ARMCPU *cpu);
#define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
#define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
#define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
+#define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */
+#define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */
+#define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */
+#define SCTLR_TMT (1ULL << 51) /* FEAT_TME */
+#define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */
+#define SCTLR_TME (1ULL << 53) /* FEAT_TME */
+#define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */
+#define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */
+#define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */
+#define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */
+#define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */
+#define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */
+#define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
+#define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */
#define CPTR_TCPAC (1U << 31)
#define CPTR_TTA (1U << 20)
--
2.25.1
- [PULL 39/61] hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic(), (continued)
- [PULL 39/61] hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic(), Peter Maydell, 2022/04/22
- [PULL 28/61] hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic, Peter Maydell, 2022/04/22
- [PULL 31/61] hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi(), Peter Maydell, 2022/04/22
- [PULL 42/61] target/arm: Update ISAR fields for ARMv8.8, Peter Maydell, 2022/04/22
- [PULL 37/61] hw/intc/arm_gicv3: Update ID and feature registers for GICv4, Peter Maydell, 2022/04/22
- [PULL 30/61] hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code, Peter Maydell, 2022/04/22
- [PULL 33/61] hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling, Peter Maydell, 2022/04/22
- [PULL 40/61] hw/arm/virt: Abstract out calculation of redistributor region capacity, Peter Maydell, 2022/04/22
- [PULL 45/61] target/arm: Change DisasContext.aarch64 to bool, Peter Maydell, 2022/04/22
- [PULL 43/61] target/arm: Update SCR_EL3 bits to ARMv8.8, Peter Maydell, 2022/04/22
- [PULL 44/61] target/arm: Update SCTLR bits to ARMv9.2,
Peter Maydell <=
- [PULL 46/61] target/arm: Change CPUArchState.aarch64 to bool, Peter Maydell, 2022/04/22
- [PULL 47/61] target/arm: Extend store_cpu_offset to take field size, Peter Maydell, 2022/04/22
- [PULL 49/61] target/arm: Change CPUArchState.thumb to bool, Peter Maydell, 2022/04/22
- [PULL 50/61] target/arm: Remove fpexc32_access, Peter Maydell, 2022/04/22
- [PULL 51/61] target/arm: Split out set_btype_raw, Peter Maydell, 2022/04/22
- [PULL 53/61] target/arm: Simplify GEN_SHIFT in translate.c, Peter Maydell, 2022/04/22
- [PULL 55/61] target/arm: Simplify aa32 DISAS_WFI, Peter Maydell, 2022/04/22
- [PULL 52/61] target/arm: Split out gen_rebuild_hflags, Peter Maydell, 2022/04/22
- [PULL 48/61] target/arm: Change DisasContext.thumb to bool, Peter Maydell, 2022/04/22
- [PULL 54/61] target/arm: Simplify gen_sar, Peter Maydell, 2022/04/22