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[PULL 51/61] target/arm: Split out set_btype_raw
From: |
Peter Maydell |
Subject: |
[PULL 51/61] target/arm: Split out set_btype_raw |
Date: |
Fri, 22 Apr 2022 11:04:22 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Common code for reset_btype and set_btype.
Use tcg_constant_i32.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 25 ++++++++++++-------------
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 1ae465687ad..13a3527345f 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -128,29 +128,28 @@ static int get_a64_user_mem_index(DisasContext *s)
return arm_to_core_mmu_idx(useridx);
}
-static void reset_btype(DisasContext *s)
+static void set_btype_raw(int val)
{
- if (s->btype != 0) {
- TCGv_i32 zero = tcg_const_i32(0);
- tcg_gen_st_i32(zero, cpu_env, offsetof(CPUARMState, btype));
- tcg_temp_free_i32(zero);
- s->btype = 0;
- }
+ tcg_gen_st_i32(tcg_constant_i32(val), cpu_env,
+ offsetof(CPUARMState, btype));
}
static void set_btype(DisasContext *s, int val)
{
- TCGv_i32 tcg_val;
-
/* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
tcg_debug_assert(val >= 1 && val <= 3);
-
- tcg_val = tcg_const_i32(val);
- tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype));
- tcg_temp_free_i32(tcg_val);
+ set_btype_raw(val);
s->btype = -1;
}
+static void reset_btype(DisasContext *s)
+{
+ if (s->btype != 0) {
+ set_btype_raw(0);
+ s->btype = 0;
+ }
+}
+
void gen_a64_set_pc_im(uint64_t val)
{
tcg_gen_movi_i64(cpu_pc, val);
--
2.25.1
- [PULL 30/61] hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code, (continued)
- [PULL 30/61] hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code, Peter Maydell, 2022/04/22
- [PULL 33/61] hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling, Peter Maydell, 2022/04/22
- [PULL 40/61] hw/arm/virt: Abstract out calculation of redistributor region capacity, Peter Maydell, 2022/04/22
- [PULL 45/61] target/arm: Change DisasContext.aarch64 to bool, Peter Maydell, 2022/04/22
- [PULL 43/61] target/arm: Update SCR_EL3 bits to ARMv8.8, Peter Maydell, 2022/04/22
- [PULL 44/61] target/arm: Update SCTLR bits to ARMv9.2, Peter Maydell, 2022/04/22
- [PULL 46/61] target/arm: Change CPUArchState.aarch64 to bool, Peter Maydell, 2022/04/22
- [PULL 47/61] target/arm: Extend store_cpu_offset to take field size, Peter Maydell, 2022/04/22
- [PULL 49/61] target/arm: Change CPUArchState.thumb to bool, Peter Maydell, 2022/04/22
- [PULL 50/61] target/arm: Remove fpexc32_access, Peter Maydell, 2022/04/22
- [PULL 51/61] target/arm: Split out set_btype_raw,
Peter Maydell <=
- [PULL 53/61] target/arm: Simplify GEN_SHIFT in translate.c, Peter Maydell, 2022/04/22
- [PULL 55/61] target/arm: Simplify aa32 DISAS_WFI, Peter Maydell, 2022/04/22
- [PULL 52/61] target/arm: Split out gen_rebuild_hflags, Peter Maydell, 2022/04/22
- [PULL 48/61] target/arm: Change DisasContext.thumb to bool, Peter Maydell, 2022/04/22
- [PULL 54/61] target/arm: Simplify gen_sar, Peter Maydell, 2022/04/22
- [PULL 56/61] target/arm: Use tcg_constant in translate-m-nocp.c, Peter Maydell, 2022/04/22
- [PULL 57/61] target/arm: Use tcg_constant in translate-neon.c, Peter Maydell, 2022/04/22
- [PULL 61/61] hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate(), Peter Maydell, 2022/04/22
- [PULL 58/61] target/arm: Use smin/smax for do_sat_addsub_32, Peter Maydell, 2022/04/22
- [PULL 41/61] hw/arm/virt: Support TCG GICv4, Peter Maydell, 2022/04/22