[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the X

From: Logan Gunthorpe
Subject: Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
Date: Wed, 21 Nov 2018 15:01:34 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1

On 2018-11-21 2:54 p.m., Alistair Francis wrote:
> The last time I tested this it worked (although I might not have
> tested interrupts) and now it doesn't. Nothing has changed in the
> series, my guest software has changed though. I can see the root
> complex, but no devices underneath it.
> Sorry for the confusion with the MicroSemi PCIe root complex.
> I think I'll just drop this patch. It doesn't work for 32-bit guests,
> but I would like to model the hardware so I don't want to change the
> addresses. We can revisit this in the future along with the gpex high
> MMIO support and USB support.

Yeah, I'm less concerned about all the board variant stuff as I am about
having something actually work. I don't want to have to jump through any
bbl hoops or anything to use it if it doesn't work out of the box. And
you're right, getting the virt pci support upstream seems more important
and this issue can be revisited later.

On an slight tangent: what root device do you use with the sifive_u
machine? I can't find any virtual hardware that works. If I had PCI I
could use NVMe, but that's not working. And for this reason I've only
been using the 'virt' device.



reply via email to

[Prev in Thread] Current Thread [Next in Thread]