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Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to
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Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree |
Date: |
Wed, 27 Feb 2019 12:27:56 -0800 (PST) |
Patchew URL: https://patchew.org/QEMU/address@hidden/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: address@hidden
Subject: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
5360362b31 target/riscv: Remaining rvc insn reuse 32 bit translators
10832a8af4 target/riscv: Splice remaining compressed insn pairs for riscv32 vs
riscv64
5571cc43be target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
564c0ac7d6 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
87b8558aa3 target/riscv: Convert @cs_2 insns to share translation functions
50437f39ef target/riscv: Remove decode_RV32_64G()
1dfbf86296 target/riscv: Remove gen_system()
db091a8aec target/riscv: Rename trans_arith to gen_arith
b2529831a9 target/riscv: Remove manual decoding of RV32/64M insn
4d9c016363 target/riscv: Remove shift and slt insn manual decoding
fa92787ed4 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
3eec88dcc5 target/riscv: Move gen_arith_imm() decoding into trans_* functions
8100a6f5fe target/riscv: Remove manual decoding from gen_store()
3272124b3a target/riscv: Remove manual decoding from gen_load()
b3587f0271 target/riscv: Remove manual decoding from gen_branch()
e11a3d3b2f target/riscv: Remove gen_jalr()
1f7c8222ef target/riscv: Convert quadrant 2 of RVXC insns to decodetree
75dad193fa target/riscv: Convert quadrant 1 of RVXC insns to decodetree
40c4217e9c target/riscv: Convert quadrant 0 of RVXC insns to decodetree
910ba2141b target/riscv: Convert RV priv insns to decodetree
e74d191af3 target/riscv: Convert RV64D insns to decodetree
059f3dc87a target/riscv: Convert RV32D insns to decodetree
4c999b97e1 target/riscv: Convert RV64F insns to decodetree
4fed7e6516 target/riscv: Convert RV32F insns to decodetree
2fc5742879 target/riscv: Convert RV64A insns to decodetree
ec8376410f target/riscv: Convert RV32A insns to decodetree
baf2143c7e target/riscv: Convert RVXM insns to decodetree
22ff1d5f7e target/riscv: Convert RVXI csr insns to decodetree
548c99a4da target/riscv: Convert RVXI fence insns to decodetree
c0b977af83 target/riscv: Convert RVXI arithmetic insns to decodetree
3a99ee7b3a target/riscv: Convert RV64I load/store insns to decodetree
bb3f7d468d target/riscv: Convert RV32I load/store insns to decodetree
56dbd0e7c1 target/riscv: Convert RVXI branch insns to decodetree
3fc565ce28 target/riscv: Activate decodetree and implemnt LUI & AUIPC
=== OUTPUT BEGIN ===
1/34 Checking commit 3fc565ce284a (target/riscv: Activate decodetree and
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1884:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 1/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/34 Checking commit 56dbd0e7c12f (target/riscv: Convert RVXI branch insns to
decodetree)
3/34 Checking commit bb3f7d468d0c (target/riscv: Convert RV32I load/store insns
to decodetree)
4/34 Checking commit 3a99ee7b3a16 (target/riscv: Convert RV64I load/store insns
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 4/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/34 Checking commit c0b977af8321 (target/riscv: Convert RVXI arithmetic insns
to decodetree)
6/34 Checking commit 548c99a4da9b (target/riscv: Convert RVXI fence insns to
decodetree)
7/34 Checking commit 22ff1d5f7e05 (target/riscv: Convert RVXI csr insns to
decodetree)
8/34 Checking commit baf2143c7ed8 (target/riscv: Convert RVXM insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 169 lines checked
Patch 8/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/34 Checking commit ec8376410f59 (target/riscv: Convert RV32A insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 199 lines checked
Patch 9/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/34 Checking commit 2fc574287901 (target/riscv: Convert RV64A insns to
decodetree)
11/34 Checking commit 4fed7e65169f (target/riscv: Convert RV32F insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 442 lines checked
Patch 11/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/34 Checking commit 4c999b97e194 (target/riscv: Convert RV64F insns to
decodetree)
13/34 Checking commit 059f3dc87a56 (target/riscv: Convert RV32D insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 398 lines checked
Patch 13/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
14/34 Checking commit e74d191af39a (target/riscv: Convert RV64D insns to
decodetree)
15/34 Checking commit 910ba2141b70 (target/riscv: Convert RV priv insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 15/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
16/34 Checking commit 40c4217e9c64 (target/riscv: Convert quadrant 0 of RVXC
insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#251: FILE: target/riscv/translate.c:1072:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 231 lines checked
Patch 16/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/34 Checking commit 75dad193fa5c (target/riscv: Convert quadrant 1 of RVXC
insns to decodetree)
18/34 Checking commit 1f7c8222efac (target/riscv: Convert quadrant 2 of RVXC
insns to decodetree)
19/34 Checking commit e11a3d3b2f9e (target/riscv: Remove gen_jalr())
20/34 Checking commit b3587f0271d0 (target/riscv: Remove manual decoding from
gen_branch())
21/34 Checking commit 3272124b3a7c (target/riscv: Remove manual decoding from
gen_load())
22/34 Checking commit 8100a6f5fe5d (target/riscv: Remove manual decoding from
gen_store())
23/34 Checking commit 3eec88dcc51f (target/riscv: Move gen_arith_imm() decoding
into trans_* functions)
24/34 Checking commit fa92787ed4c7 (target/riscv: make ADD/SUB/OR/XOR/AND insn
use arg lists)
25/34 Checking commit 4d9c0163635c (target/riscv: Remove shift and slt insn
manual decoding)
26/34 Checking commit b2529831a916 (target/riscv: Remove manual decoding of
RV32/64M insn)
27/34 Checking commit db091a8aec70 (target/riscv: Rename trans_arith to
gen_arith)
28/34 Checking commit 1dfbf862969a (target/riscv: Remove gen_system())
29/34 Checking commit 50437f39ef7a (target/riscv: Remove decode_RV32_64G())
30/34 Checking commit 87b8558aa3ce (target/riscv: Convert @cs_2 insns to share
translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:548:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 30/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
31/34 Checking commit 564c0ac7d659 (target/riscv: Convert @cl_d, @cl_w, @cs_d,
@cs_w insns)
32/34 Checking commit 5571cc43beef (target/riscv: Splice fsw_sd and flw_ld for
riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 309 lines checked
Patch 32/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
33/34 Checking commit 10832a8af42c (target/riscv: Splice remaining compressed
insn pairs for riscv32 vs riscv64)
34/34 Checking commit 5360362b3101 (target/riscv: Remaining rvc insn reuse 32
bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to address@hidden
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- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
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- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
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