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[PULL 27/43] target/mips: Use GPR move functions in gen_HILO1_tx79()
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 27/43] target/mips: Use GPR move functions in gen_HILO1_tx79() |
Date: |
Sun, 21 Feb 2021 15:34:16 +0100 |
We have handy functions to access GPR. Use gen_store_gpr() for
Move From HI/LO Register and gen_load_gpr() for Move To opcodes.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-8-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 21 ++++-----------------
1 file changed, 4 insertions(+), 17 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a303c36be3f..70891c37cdd 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4126,31 +4126,18 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
/* Copy GPR to and from TX79 HI1/LO1 register. */
static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
{
- if (reg == 0 && (opc == MMI_OPC_MFHI1 || opc == MMI_OPC_MFLO1)) {
- /* Treat as NOP. */
- return;
- }
-
switch (opc) {
case MMI_OPC_MFHI1:
- tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[1]);
+ gen_store_gpr(cpu_HI[1], reg);
break;
case MMI_OPC_MFLO1:
- tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[1]);
+ gen_store_gpr(cpu_LO[1], reg);
break;
case MMI_OPC_MTHI1:
- if (reg != 0) {
- tcg_gen_mov_tl(cpu_HI[1], cpu_gpr[reg]);
- } else {
- tcg_gen_movi_tl(cpu_HI[1], 0);
- }
+ gen_load_gpr(cpu_HI[1], reg);
break;
case MMI_OPC_MTLO1:
- if (reg != 0) {
- tcg_gen_mov_tl(cpu_LO[1], cpu_gpr[reg]);
- } else {
- tcg_gen_movi_tl(cpu_LO[1], 0);
- }
+ gen_load_gpr(cpu_LO[1], reg);
break;
default:
MIPS_INVAL("mfthilo1 TX79");
--
2.26.2
- [PULL 21/43] target/mips: Remove unused 'rw' argument from page_table_walk_refill(), (continued)
- [PULL 21/43] target/mips: Remove unused 'rw' argument from page_table_walk_refill(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 22/43] target/mips: Include missing "tcg/tcg.h" header, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 23/43] target/mips: Make cpu_HI/LO registers public, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 25/43] target/mips: Rename 128-bit upper halve GPR registers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 29/43] vt82c686: Reorganise code, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 28/43] vt82c686: Move superio memory region to SuperIOConfig struct, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 24/43] target/mips: Promote 128-bit multimedia registers as global ones, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 31/43] vt82c686: Make vt82c686-pm an I/O tracing region, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 26/43] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 32/43] vt82c686: Correct vt82c686-pm I/O size, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 27/43] target/mips: Use GPR move functions in gen_HILO1_tx79(),
Philippe Mathieu-Daudé <=
- [PULL 30/43] vt82c686: Fix SMBus IO base and configuration registers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 33/43] vt82c686: Correctly reset all registers to default values on reset, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 34/43] vt82c686: Fix up power management io base and config, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 35/43] vt82c686: Set user_creatable=false for VT82C686B_PM, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 36/43] vt82c686: Make vt82c686b-pm an abstract base class and add vt8231-pm based on it, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 37/43] vt82c686: Simplify vt82c686b_realize(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 38/43] vt82c686: Move creation of ISA devices to the ISA bridge, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 39/43] vt82c686: Remove index field of SuperIOConfig, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 40/43] vt82c686: Reduce indentation by returning early, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 42/43] vt82c686: Log superio_cfg unimplemented accesses, Philippe Mathieu-Daudé, 2021/02/21