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[PULL 26/43] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 26/43] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers |
Date: |
Sun, 21 Feb 2021 15:34:15 +0100 |
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-7-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 4 ++++
target/mips/translate.c | 18 ++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 3014c20cadb..468e29d7578 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -131,6 +131,10 @@ void gen_move_low32(TCGv ret, TCGv_i64 arg);
void gen_move_high32(TCGv ret, TCGv_i64 arg);
void gen_load_gpr(TCGv t, int reg);
void gen_store_gpr(TCGv t, int reg);
+#if defined(TARGET_MIPS64)
+void gen_load_gpr_hi(TCGv_i64 t, int reg);
+void gen_store_gpr_hi(TCGv_i64 t, int reg);
+#endif /* TARGET_MIPS64 */
void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5228e040842..a303c36be3f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2291,6 +2291,24 @@ void gen_store_gpr(TCGv t, int reg)
}
}
+#if defined(TARGET_MIPS64)
+void gen_load_gpr_hi(TCGv_i64 t, int reg)
+{
+ if (reg == 0) {
+ tcg_gen_movi_i64(t, 0);
+ } else {
+ tcg_gen_mov_i64(t, cpu_gpr_hi[reg]);
+ }
+}
+
+void gen_store_gpr_hi(TCGv_i64 t, int reg)
+{
+ if (reg != 0) {
+ tcg_gen_mov_i64(cpu_gpr_hi[reg], t);
+ }
+}
+#endif /* TARGET_MIPS64 */
+
/* Moves to/from shadow registers. */
static inline void gen_load_srsgpr(int from, int to)
{
--
2.26.2
- [PULL 19/43] target/mips: Let get_seg*_physical_address() take MMUAccessType arg, (continued)
- [PULL 19/43] target/mips: Let get_seg*_physical_address() take MMUAccessType arg, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 20/43] target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 21/43] target/mips: Remove unused 'rw' argument from page_table_walk_refill(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 22/43] target/mips: Include missing "tcg/tcg.h" header, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 23/43] target/mips: Make cpu_HI/LO registers public, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 25/43] target/mips: Rename 128-bit upper halve GPR registers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 29/43] vt82c686: Reorganise code, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 28/43] vt82c686: Move superio memory region to SuperIOConfig struct, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 24/43] target/mips: Promote 128-bit multimedia registers as global ones, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 31/43] vt82c686: Make vt82c686-pm an I/O tracing region, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 26/43] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers,
Philippe Mathieu-Daudé <=
- [PULL 32/43] vt82c686: Correct vt82c686-pm I/O size, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 27/43] target/mips: Use GPR move functions in gen_HILO1_tx79(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 30/43] vt82c686: Fix SMBus IO base and configuration registers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 33/43] vt82c686: Correctly reset all registers to default values on reset, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 34/43] vt82c686: Fix up power management io base and config, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 35/43] vt82c686: Set user_creatable=false for VT82C686B_PM, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 36/43] vt82c686: Make vt82c686b-pm an abstract base class and add vt8231-pm based on it, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 37/43] vt82c686: Simplify vt82c686b_realize(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 38/43] vt82c686: Move creation of ISA devices to the ISA bridge, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 39/43] vt82c686: Remove index field of SuperIOConfig, Philippe Mathieu-Daudé, 2021/02/21