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[PULL 25/43] target/mips: Rename 128-bit upper halve GPR registers
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PULL 25/43] target/mips: Rename 128-bit upper halve GPR registers |
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Date: |
Sun, 21 Feb 2021 15:34:14 +0100 |
TCG displays the upper halve registers with the same name
as their lower halves. Rename the upper halves with the
'[hi]' suffix.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-6-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2df76592470..5228e040842 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29289,10 +29289,12 @@ void mips_tcg_init(void)
cpu_gpr_hi[0] = NULL;
for (unsigned i = 1; i < 32; i++) {
+ g_autofree char *rname = g_strdup_printf("%s[hi]", regnames[i]);
+
cpu_gpr_hi[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUMIPSState,
active_tc.gpr_hi[i]),
- regnames[i]);
+ rname);
}
#endif /* !TARGET_MIPS64 */
for (i = 0; i < 32; i++) {
--
2.26.2
- [PULL 14/43] target/mips: Replace magic value by MMU_DATA_LOAD definition, (continued)
- [PULL 14/43] target/mips: Replace magic value by MMU_DATA_LOAD definition, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 15/43] target/mips: Let do_translate_address() take MMUAccessType argument, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 16/43] target/mips: Let cpu_mips_translate_address() take MMUAccessType arg, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 17/43] target/mips: Let raise_mmu_exception() take MMUAccessType argument, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 18/43] target/mips: Let get_physical_address() take MMUAccessType argument, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 19/43] target/mips: Let get_seg*_physical_address() take MMUAccessType arg, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 20/43] target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 21/43] target/mips: Remove unused 'rw' argument from page_table_walk_refill(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 22/43] target/mips: Include missing "tcg/tcg.h" header, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 23/43] target/mips: Make cpu_HI/LO registers public, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 25/43] target/mips: Rename 128-bit upper halve GPR registers,
Philippe Mathieu-Daudé <=
- [PULL 29/43] vt82c686: Reorganise code, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 28/43] vt82c686: Move superio memory region to SuperIOConfig struct, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 24/43] target/mips: Promote 128-bit multimedia registers as global ones, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 31/43] vt82c686: Make vt82c686-pm an I/O tracing region, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 26/43] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 32/43] vt82c686: Correct vt82c686-pm I/O size, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 27/43] target/mips: Use GPR move functions in gen_HILO1_tx79(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 30/43] vt82c686: Fix SMBus IO base and configuration registers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 33/43] vt82c686: Correctly reset all registers to default values on reset, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 34/43] vt82c686: Fix up power management io base and config, Philippe Mathieu-Daudé, 2021/02/21