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[PULL 24/43] target/mips: Promote 128-bit multimedia registers as global
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 24/43] target/mips: Promote 128-bit multimedia registers as global ones |
Date: |
Sun, 21 Feb 2021 15:34:13 +0100 |
The cpu::mmr[] array contains the upper halves of 128-bit GPR
registers. While they are only used by the R5900 CPU, the
concept is generic and could be used by another MIPS implementation.
Rename 'cpu::mmr' as 'cpu::gpr_hi' and make them global.
When the code is similar to the GPR lower halves, move it
close by.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-5-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.h | 10 ++++++---
target/mips/translate.h | 3 +++
target/mips/translate.c | 48 ++++++++++++++++++++---------------------
3 files changed, 34 insertions(+), 27 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 9e6028f8e63..075c24abdad 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -460,6 +460,13 @@ typedef struct mips_def_t mips_def_t;
typedef struct TCState TCState;
struct TCState {
target_ulong gpr[32];
+#if defined(TARGET_MIPS64)
+ /*
+ * For CPUs using 128-bit GPR registers, we put the lower halves in gpr[])
+ * and the upper halves in gpr_hi[].
+ */
+ uint64_t gpr_hi[32];
+#endif /* TARGET_MIPS64 */
target_ulong PC;
target_ulong HI[MIPS_DSP_ACC];
target_ulong LO[MIPS_DSP_ACC];
@@ -505,9 +512,6 @@ struct TCState {
float_status msa_fp_status;
- /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */
- uint64_t mmr[32];
-
#define NUMBER_OF_MXU_REGISTERS 16
target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
target_ulong mxu_cr;
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 2a1d8f570bb..3014c20cadb 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -145,6 +145,9 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int
sa);
bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
extern TCGv cpu_gpr[32], cpu_PC;
+#if defined(TARGET_MIPS64)
+extern TCGv_i64 cpu_gpr_hi[32];
+#endif
extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
extern TCGv_i32 fpu_fcr0, fpu_fcr31;
extern TCGv_i64 fpu_f64[32];
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c20f630b7e7..2df76592470 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2179,6 +2179,11 @@ enum {
/* global register indices */
TCGv cpu_gpr[32], cpu_PC;
+/*
+ * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gpr[])
+ * and the upper halves in cpu_gpr_hi[].
+ */
+TCGv_i64 cpu_gpr_hi[32];
TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
static TCGv cpu_dspctrl, btarget;
TCGv bcond;
@@ -2187,11 +2192,6 @@ static TCGv_i32 hflags;
TCGv_i32 fpu_fcr0, fpu_fcr31;
TCGv_i64 fpu_f64[32];
-#if defined(TARGET_MIPS64)
-/* Upper halves of R5900's 128-bit registers: MMRs (multimedia registers) */
-static TCGv_i64 cpu_mmr[32];
-#endif
-
#if !defined(TARGET_MIPS64)
/* MXU registers */
static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
@@ -24784,7 +24784,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
/* nop */
} else if (rt == 0) {
tcg_gen_movi_i64(cpu_gpr[rd], 0);
- tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
} else {
TCGv_i64 t0 = tcg_temp_new();
TCGv_i64 t1 = tcg_temp_new();
@@ -24802,7 +24802,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
tcg_gen_mov_i64(cpu_gpr[rd], t1);
- tcg_gen_andi_i64(t0, cpu_mmr[rt], mask);
+ tcg_gen_andi_i64(t0, cpu_gpr_hi[rt], mask);
tcg_gen_movi_i64(t1, 0);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_shli_i64(t0, t0, 16);
@@ -24812,7 +24812,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
tcg_gen_shli_i64(t0, t0, 16);
tcg_gen_or_i64(t1, t0, t1);
- tcg_gen_mov_i64(cpu_mmr[rd], t1);
+ tcg_gen_mov_i64(cpu_gpr_hi[rd], t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
@@ -24844,9 +24844,9 @@ static void gen_mmi_pcpyld(DisasContext *ctx)
/* nop */
} else {
if (rs == 0) {
- tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
} else {
- tcg_gen_mov_i64(cpu_mmr[rd], cpu_gpr[rs]);
+ tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr[rs]);
}
if (rt == 0) {
tcg_gen_movi_i64(cpu_gpr[rd], 0);
@@ -24885,13 +24885,13 @@ static void gen_mmi_pcpyud(DisasContext *ctx)
if (rs == 0) {
tcg_gen_movi_i64(cpu_gpr[rd], 0);
} else {
- tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
+ tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr_hi[rs]);
}
if (rt == 0) {
- tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
} else {
if (rd != rt) {
- tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
+ tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt]);
}
}
}
@@ -29285,6 +29285,16 @@ void mips_tcg_init(void)
offsetof(CPUMIPSState,
active_tc.gpr[i]),
regnames[i]);
+#if defined(TARGET_MIPS64)
+ cpu_gpr_hi[0] = NULL;
+
+ for (unsigned i = 1; i < 32; i++) {
+ cpu_gpr_hi[i] = tcg_global_mem_new_i64(cpu_env,
+ offsetof(CPUMIPSState,
+ active_tc.gpr_hi[i]),
+ regnames[i]);
+ }
+#endif /* !TARGET_MIPS64 */
for (i = 0; i < 32; i++) {
int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
@@ -29323,16 +29333,6 @@ void mips_tcg_init(void)
cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval),
"llval");
-#if defined(TARGET_MIPS64)
- cpu_mmr[0] = NULL;
- for (i = 1; i < 32; i++) {
- cpu_mmr[i] = tcg_global_mem_new_i64(cpu_env,
- offsetof(CPUMIPSState,
- active_tc.mmr[i]),
- regnames[i]);
- }
-#endif
-
#if !defined(TARGET_MIPS64)
for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
mxu_gpr[i] = tcg_global_mem_new(cpu_env,
@@ -29344,7 +29344,7 @@ void mips_tcg_init(void)
mxu_CR = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState, active_tc.mxu_cr),
mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
-#endif
+#endif /* !TARGET_MIPS64 */
}
void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,
--
2.26.2
- [PULL 17/43] target/mips: Let raise_mmu_exception() take MMUAccessType argument, (continued)
- [PULL 17/43] target/mips: Let raise_mmu_exception() take MMUAccessType argument, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 18/43] target/mips: Let get_physical_address() take MMUAccessType argument, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 19/43] target/mips: Let get_seg*_physical_address() take MMUAccessType arg, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 20/43] target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 21/43] target/mips: Remove unused 'rw' argument from page_table_walk_refill(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 22/43] target/mips: Include missing "tcg/tcg.h" header, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 23/43] target/mips: Make cpu_HI/LO registers public, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 25/43] target/mips: Rename 128-bit upper halve GPR registers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 29/43] vt82c686: Reorganise code, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 28/43] vt82c686: Move superio memory region to SuperIOConfig struct, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 24/43] target/mips: Promote 128-bit multimedia registers as global ones,
Philippe Mathieu-Daudé <=
- [PULL 31/43] vt82c686: Make vt82c686-pm an I/O tracing region, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 26/43] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 32/43] vt82c686: Correct vt82c686-pm I/O size, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 27/43] target/mips: Use GPR move functions in gen_HILO1_tx79(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 30/43] vt82c686: Fix SMBus IO base and configuration registers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 33/43] vt82c686: Correctly reset all registers to default values on reset, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 34/43] vt82c686: Fix up power management io base and config, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 35/43] vt82c686: Set user_creatable=false for VT82C686B_PM, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 36/43] vt82c686: Make vt82c686b-pm an abstract base class and add vt8231-pm based on it, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 37/43] vt82c686: Simplify vt82c686b_realize(), Philippe Mathieu-Daudé, 2021/02/21