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[PULL 32/43] vt82c686: Correct vt82c686-pm I/O size
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PULL 32/43] vt82c686: Correct vt82c686-pm I/O size |
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Date: |
Sun, 21 Feb 2021 15:34:21 +0100 |
From: BALATON Zoltan <balaton@eik.bme.hu>
Section "Offset 4B-48 – Power Management I/O Base" describes:
Port Address for the base of the 128-byte Power
Management I/O Register block.
Correct the vt82c686-pm I/O region size.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu>
[PMD: Split original patch, this is part 2/4, reduced size to 128B]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/isa/vt82c686.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 7e6a07fca48..fe8ae24c421 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -176,7 +176,7 @@ static void vt82c686b_pm_realize(PCIDevice *dev, Error
**errp)
apm_init(dev, &s->apm, NULL, s);
memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s,
- "vt82c686-pm", 64);
+ "vt82c686-pm", 128);
memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io);
memory_region_set_enabled(&s->io, false);
--
2.26.2
- [PULL 20/43] target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType, (continued)
- [PULL 20/43] target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 21/43] target/mips: Remove unused 'rw' argument from page_table_walk_refill(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 22/43] target/mips: Include missing "tcg/tcg.h" header, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 23/43] target/mips: Make cpu_HI/LO registers public, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 25/43] target/mips: Rename 128-bit upper halve GPR registers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 29/43] vt82c686: Reorganise code, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 28/43] vt82c686: Move superio memory region to SuperIOConfig struct, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 24/43] target/mips: Promote 128-bit multimedia registers as global ones, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 31/43] vt82c686: Make vt82c686-pm an I/O tracing region, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 26/43] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 32/43] vt82c686: Correct vt82c686-pm I/O size,
Philippe Mathieu-Daudé <=
- [PULL 27/43] target/mips: Use GPR move functions in gen_HILO1_tx79(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 30/43] vt82c686: Fix SMBus IO base and configuration registers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 33/43] vt82c686: Correctly reset all registers to default values on reset, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 34/43] vt82c686: Fix up power management io base and config, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 35/43] vt82c686: Set user_creatable=false for VT82C686B_PM, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 36/43] vt82c686: Make vt82c686b-pm an abstract base class and add vt8231-pm based on it, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 37/43] vt82c686: Simplify vt82c686b_realize(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 38/43] vt82c686: Move creation of ISA devices to the ISA bridge, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 39/43] vt82c686: Remove index field of SuperIOConfig, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 40/43] vt82c686: Reduce indentation by returning early, Philippe Mathieu-Daudé, 2021/02/21