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[PULL 22/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CP
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 22/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5) |
Date: |
Fri, 13 Jan 2023 16:45:08 +0100 |
Part 5/5: Convert jumping to kernel
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-11-philmd@linaro.org>
---
hw/mips/malta.c | 68 ++++++++-----------------------------------------
1 file changed, 11 insertions(+), 57 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index e618513e35..b66dad0510 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -625,11 +625,6 @@ static void write_bootloader_nanomips(uint8_t *base,
uint64_t run_addr,
/* Small bootloader */
p = (uint16_t *)base;
-#define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
-#define NM_HI2(VAL) \
- (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
-#define NM_LO(VAL) ((VAL) & 0xfff)
-
stw_p(p++, 0x2800); stw_p(p++, 0x001c);
/* bc to_here */
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
@@ -648,46 +643,6 @@ static void write_bootloader_nanomips(uint8_t *base,
uint64_t run_addr,
/* nop */
/* to_here: */
- if (semihosting_get_argc()) {
- /* Preserve a0 content as arguments have been passed */
- stw_p(p++, 0x8000); stw_p(p++, 0xc000);
- /* nop */
- } else {
- stw_p(p++, 0x0080); stw_p(p++, 0x0002);
- /* li a0,2 */
- }
-
- stw_p(p++, 0xe3a0 | NM_HI1(ENVP_VADDR - 64));
-
- stw_p(p++, NM_HI2(ENVP_VADDR - 64));
- /* lui sp,%hi(ENVP_VADDR - 64) */
-
- stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_VADDR - 64));
- /* ori sp,sp,%lo(ENVP_VADDR - 64) */
-
- stw_p(p++, 0xe0a0 | NM_HI1(ENVP_VADDR));
-
- stw_p(p++, NM_HI2(ENVP_VADDR));
- /* lui a1,%hi(ENVP_VADDR) */
-
- stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_VADDR));
- /* ori a1,a1,%lo(ENVP_VADDR) */
-
- stw_p(p++, 0xe0c0 | NM_HI1(ENVP_VADDR + 8));
-
- stw_p(p++, NM_HI2(ENVP_VADDR + 8));
- /* lui a2,%hi(ENVP_VADDR + 8) */
-
- stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_VADDR + 8));
- /* ori a2,a2,%lo(ENVP_VADDR + 8) */
-
- stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size));
-
- stw_p(p++, NM_HI2(loaderparams.ram_low_size));
- /* lui a3,%hi(loaderparams.ram_low_size) */
-
- stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
- /* ori a3,a3,%lo(loaderparams.ram_low_size) */
#if TARGET_BIG_ENDIAN
#define cpu_to_gt32 cpu_to_le32
@@ -725,20 +680,19 @@ static void write_bootloader_nanomips(uint8_t *base,
uint64_t run_addr,
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
cpu_to_gt32(0x0bc00000 << 3));
- p = v;
-
#undef cpu_to_gt32
- stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
-
- stw_p(p++, NM_HI2(kernel_entry));
- /* lui t9,%hi(kernel_entry) */
-
- stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry));
- /* ori t9,t9,%lo(kernel_entry) */
-
- stw_p(p++, 0x4bf9); stw_p(p++, 0x0000);
- /* jalrc t8 */
+ bl_gen_jump_kernel(&v,
+ true, ENVP_VADDR - 64,
+ /*
+ * If semihosting is used, arguments have already been
+ * passed, so we preserve $a0.
+ */
+ !semihosting_get_argc(), 2,
+ true, ENVP_VADDR,
+ true, ENVP_VADDR + 8,
+ true, loaderparams.ram_low_size,
+ kernel_entry);
}
/*
--
2.38.1
- [PULL 14/46] hw/mips/bootloader: Implement nanoMIPS NOP opcode generator, (continued)
- [PULL 14/46] hw/mips/bootloader: Implement nanoMIPS NOP opcode generator, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 08/46] hw/mips/gt64xxx_pci: Add a 'cpu-little-endian' qdev property, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 12/46] tests/avocado: Add tests booting YAMON ROM on MIPS Malta machines, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 15/46] hw/mips/bootloader: Implement nanoMIPS SW opcode generator, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 16/46] hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) opcode generator, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 17/46] hw/mips/bootloader: Implement nanoMIPS JALRc opcode generator, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 18/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (1/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 19/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (2/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 20/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 21/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (4/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 22/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5),
Philippe Mathieu-Daudé <=
- [PULL 23/46] hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel(), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 24/46] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 25/46] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 26/46] hw/isa/piix4: Correct IRQRC[A:D] reset values, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 27/46] mips: Remove support for trap and emulate KVM, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 28/46] mips: Always include nanomips disassembler, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 29/46] hw/pci/pci_host: Trace config accesses on unexisting functions, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 30/46] hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs(), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 31/46] hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 32/46] hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific, Philippe Mathieu-Daudé, 2023/01/13