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[PULL 16/46] hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) opcode
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 16/46] hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) opcode generator |
Date: |
Fri, 13 Jan 2023 16:45:02 +0100 |
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-5-philmd@linaro.org>
---
hw/mips/bootloader.c | 36 ++++++++++++++++++++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 3e1e73360f..9fc926d83f 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -132,12 +132,39 @@ static void bl_gen_jalr(void **p, bl_reg rs)
bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
}
+static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20)
+{
+ uint32_t insn = 0;
+
+ assert(extract32(imm20, 0, 20) == imm20);
+ insn = deposit32(insn, 26, 6, 0b111000);
+ insn = deposit32(insn, 21, 5, rt);
+ insn = deposit32(insn, 12, 9, extract32(imm20, 0, 9));
+ insn = deposit32(insn, 2, 10, extract32(imm20, 9, 10));
+ insn = deposit32(insn, 0, 1, sextract32(imm20, 19, 1));
+
+ st_nm32_p(ptr, insn);
+}
+
static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm)
{
/* R6: It's a alias of AUI with RS = 0 */
bl_gen_i_type(p, 0x0f, 0, rt, imm);
}
+static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm12)
+{
+ uint32_t insn = 0;
+
+ assert(extract32(imm12, 0, 12) == imm12);
+ insn = deposit32(insn, 26, 6, 0b100000);
+ insn = deposit32(insn, 21, 5, rt);
+ insn = deposit32(insn, 16, 5, rs);
+ insn = deposit32(insn, 0, 12, imm12);
+
+ st_nm32_p(ptr, insn);
+}
+
static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
{
bl_gen_i_type(p, 0x0d, rs, rt, imm);
@@ -178,8 +205,13 @@ static void bl_gen_sd(void **p, bl_reg rt, uint8_t base,
uint16_t offset)
/* Pseudo instructions */
static void bl_gen_li(void **p, bl_reg rt, uint32_t imm)
{
- bl_gen_lui(p, rt, extract32(imm, 16, 16));
- bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
+ if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+ bl_gen_lui_nm(p, rt, extract32(imm, 12, 20));
+ bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12));
+ } else {
+ bl_gen_lui(p, rt, extract32(imm, 16, 16));
+ bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
+ }
}
static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm)
--
2.38.1
- [PULL 06/46] hw/mips/gt64xxx_pci: Let the GT64120 manage the lower 512MiB hole, (continued)
- [PULL 06/46] hw/mips/gt64xxx_pci: Let the GT64120 manage the lower 512MiB hole, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 07/46] hw/mips/gt64xxx_pci: Manage endian bits with the RegisterFields API, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 13/46] hw/mips/bootloader: Handle buffers as opaque arrays, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 09/46] hw/mips/malta: Explicit GT64120 endianness upon device creation, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 10/46] hw/mips/meson: Make gt64xxx_pci.c endian-agnostic, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 11/46] hw/mips/gt64xxx_pci: Move it to hw/pci-host/, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 14/46] hw/mips/bootloader: Implement nanoMIPS NOP opcode generator, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 08/46] hw/mips/gt64xxx_pci: Add a 'cpu-little-endian' qdev property, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 12/46] tests/avocado: Add tests booting YAMON ROM on MIPS Malta machines, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 15/46] hw/mips/bootloader: Implement nanoMIPS SW opcode generator, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 16/46] hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) opcode generator,
Philippe Mathieu-Daudé <=
- [PULL 17/46] hw/mips/bootloader: Implement nanoMIPS JALRc opcode generator, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 18/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (1/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 19/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (2/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 20/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 21/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (4/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 22/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 23/46] hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel(), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 24/46] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 25/46] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 26/46] hw/isa/piix4: Correct IRQRC[A:D] reset values, Philippe Mathieu-Daudé, 2023/01/13