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[PULL 20/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CP
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 20/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5) |
Date: |
Fri, 13 Jan 2023 16:45:06 +0100 |
Part 3/5: Convert PCI0 I/O BAR setup
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-9-philmd@linaro.org>
---
hw/mips/malta.c | 40 ++++++++--------------------------------
1 file changed, 8 insertions(+), 32 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 7d0fc5d0c8..f0ed32167f 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -691,9 +691,6 @@ static void write_bootloader_nanomips(uint8_t *base,
uint64_t run_addr,
/*
* Load BAR registers as done by YAMON:
- *
- * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
- *
*/
stw_p(p++, 0xe040); stw_p(p++, 0x0681);
/* lui t1, %hi(0xb4000000) */
@@ -713,21 +710,6 @@ static void write_bootloader_nanomips(uint8_t *base,
uint64_t run_addr,
stw_p(p++, 0xe020); stw_p(p++, 0x0801);
/* lui t0, %hi(0xc0000000) */
-
- /* 0x48 corresponds to GT_PCI0IOLD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9048);
- /* sw t0, 0x48(t1) */
-
- stw_p(p++, 0xe020); stw_p(p++, 0x0800);
- /* lui t0, %hi(0x40000000) */
-
- /* 0x50 corresponds to GT_PCI0IOHD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9050);
- /* sw t0, 0x50(t1) */
-
- stw_p(p++, 0xe020); stw_p(p++, 0x0001);
- /* lui t0, %hi(0x80000000) */
-
#else
#define cpu_to_gt32 cpu_to_be32
@@ -744,23 +726,17 @@ static void write_bootloader_nanomips(uint8_t *base,
uint64_t run_addr,
stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
/* addiu[32] t0, $0, 0xc0 */
-
- /* 0x48 corresponds to GT_PCI0IOLD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9048);
- /* sw t0, 0x48(t1) */
-
- stw_p(p++, 0x0020); stw_p(p++, 0x0040);
- /* addiu[32] t0, $0, 0x40 */
-
- /* 0x50 corresponds to GT_PCI0IOHD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9050);
- /* sw t0, 0x50(t1) */
-
- stw_p(p++, 0x0020); stw_p(p++, 0x0080);
- /* addiu[32] t0, $0, 0x80 */
#endif
v = p;
+ /* setup PCI0 io window to 0x18000000-0x181fffff */
+ bl_gen_write_u32(&v, /* GT_PCI0IOLD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
+ cpu_to_gt32(0x18000000 << 3));
+ bl_gen_write_u32(&v, /* GT_PCI0IOHD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
+ cpu_to_gt32(0x08000000 << 3));
+
/* setup PCI0 mem windows */
bl_gen_write_u32(&v, /* GT_PCI0M0LD */
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
--
2.38.1
- [PULL 10/46] hw/mips/meson: Make gt64xxx_pci.c endian-agnostic, (continued)
- [PULL 10/46] hw/mips/meson: Make gt64xxx_pci.c endian-agnostic, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 11/46] hw/mips/gt64xxx_pci: Move it to hw/pci-host/, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 14/46] hw/mips/bootloader: Implement nanoMIPS NOP opcode generator, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 08/46] hw/mips/gt64xxx_pci: Add a 'cpu-little-endian' qdev property, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 12/46] tests/avocado: Add tests booting YAMON ROM on MIPS Malta machines, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 15/46] hw/mips/bootloader: Implement nanoMIPS SW opcode generator, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 16/46] hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) opcode generator, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 17/46] hw/mips/bootloader: Implement nanoMIPS JALRc opcode generator, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 18/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (1/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 19/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (2/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 20/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5),
Philippe Mathieu-Daudé <=
- [PULL 21/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (4/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 22/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 23/46] hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel(), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 24/46] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 25/46] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 26/46] hw/isa/piix4: Correct IRQRC[A:D] reset values, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 27/46] mips: Remove support for trap and emulate KVM, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 28/46] mips: Always include nanomips disassembler, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 29/46] hw/pci/pci_host: Trace config accesses on unexisting functions, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 30/46] hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs(), Philippe Mathieu-Daudé, 2023/01/13