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[PULL 26/46] hw/isa/piix4: Correct IRQRC[A:D] reset values
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 26/46] hw/isa/piix4: Correct IRQRC[A:D] reset values |
Date: |
Fri, 13 Jan 2023 16:45:12 +0100 |
IRQRC[A:D] registers reset value is 0x80. We were forcing
the MIPS Malta machine routing to be able to boot a Linux
kernel without any bootloader.
We now have these registers initialized in the Malta machine
write_bootloader(), so we can use the correct reset values.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221027204720.33611-4-philmd@linaro.org>
---
hw/isa/piix4.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 8fc1db6dc9..0d23e11a39 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -116,10 +116,10 @@ static void piix4_isa_reset(DeviceState *dev)
pci_conf[0x4c] = 0x4d;
pci_conf[0x4e] = 0x03;
pci_conf[0x4f] = 0x00;
- pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
- pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
- pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
- pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
+ pci_conf[0x60] = 0x80;
+ pci_conf[0x61] = 0x80;
+ pci_conf[0x62] = 0x80;
+ pci_conf[0x63] = 0x80;
pci_conf[0x69] = 0x02;
pci_conf[0x70] = 0x80;
pci_conf[0x76] = 0x0c;
--
2.38.1
- [PULL 16/46] hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) opcode generator, (continued)
- [PULL 16/46] hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) opcode generator, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 17/46] hw/mips/bootloader: Implement nanoMIPS JALRc opcode generator, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 18/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (1/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 19/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (2/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 20/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 21/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (4/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 22/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 23/46] hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel(), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 24/46] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 25/46] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 26/46] hw/isa/piix4: Correct IRQRC[A:D] reset values,
Philippe Mathieu-Daudé <=
- [PULL 27/46] mips: Remove support for trap and emulate KVM, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 28/46] mips: Always include nanomips disassembler, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 29/46] hw/pci/pci_host: Trace config accesses on unexisting functions, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 30/46] hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs(), Philippe Mathieu-Daudé, 2023/01/13
- [PULL 31/46] hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 32/46] hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 33/46] hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 35/46] hw/intc/i8259: Make using the isa_pic singleton more type-safe, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 34/46] hw/usb/hcd-uhci: Introduce TYPE_ defines for device models, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 36/46] hw/intc: Extract the IRQ counting functions into a separate file, Philippe Mathieu-Daudé, 2023/01/13